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19-3690; Rev 0; 6/05
KIT ATION EVALU ABLE AVAIL
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator
General Description Features
Internal 8m On-Resistance MOSFETs 10A Output PWM Step-Down Regulator 1% Output Accuracy over Load, Line, and Temperature Operates from 2.3V to 3.6V Input Supply Adjustable Output from 0.6V to (0.87 x VIN) 250kHz to 2.4MHz Adjustable Frequency or SYNC Input Allows All-Ceramic-Capacitor Design SYNCOUT Drives 2nd Regulator 180 Out-of-Phase Prebiased or Monotonic Soft-Start Programmable Soft-Start Time Output Tracking or Sequencing Sourcing and Sinking Output Current Power-Good Output 32-Lead Thin QFN Package REFIN for DDR-Termination Application
MAX8566
The MAX8566 high-efficiency switching regulator delivers up to 10A load current at output voltages from 0.6V to (0.87 x VIN). The IC operates from 2.3V to 3.6V input supplies, making it ideal for point-of-load applications. The total output-voltage set error is less than 1% over load, line, and temperature. The MAX8566 operates in pulse-width-modulation (PWM) mode with a 250kHz to 2.4MHz switching frequency range that is programmable by an external resistor. The IC can be synchronized to an external clock in the same frequency range using the SYNC input. The high operating frequency minimizes the size of external components. Using low-RDS(ON) n-channel MOSFETs for both high- and low-side switches maintains high efficiency at both heavy-load and highswitching frequencies. The MAX8566 employs a voltage-mode control architecture with a high-bandwidth (> 10MHz) error amplifier. The voltage-mode control architecture makes switching frequencies greater than 1MHz possible, achieving all-ceramic-capacitor designs to minimize PC board space. The error amplifier works with Type 3 compensation to fully utilize the bandwidth of the highfrequency switching to obtain fast transient response. Adjustable soft-start time provides flexibility to minimize input startup inrush current. An open-drain, powergood (PWRGD) signal goes high when the output reaches 90% of its regulation point. The MAX8566 provides a SYNCOUT output to synchronize a second MAX8566 or a second regulator switching 180 out-of-phase with the first to reduce the input ripple current, which consequently reduces the inputcapacitance requirements. The MAX8566 also provides an external reference input (REFIN) for output-tracking applications. The MAX8566 is available in a 32-pin, 5mm x 5mm thin QFN package. The MAX8566 and all the required external components fit into a footprint of less than 0.80in2.
Ordering Information
PART MAX8566ETJ+ TEMP RANGE -40C to +85C PIN-PACKAGE 32 Thin QFN 5mm x 5mm (T3255-4)
+Denotes lead-free package.
Typical Operating Circuit
INPUT 2.25V TO 3.6V
VDD
LSS IN
IN
IN
IN
IN
REFIN FOR TRACKING
REFIN SS
SYSTEM ENABLE SYNC INPUT PROGRAMMABLE FREQUENCY SYNC OUTPUT 180
EN SYNC FREQ SYNCOUT GND
MAX8566ETJ+ STEP-DOWN REGULATOR TQFN 5mm x 5mm
PGND
PGND PGND PGND PGND LX LX LX L1 330nH/10A OUTPUT UP TO 10A C5 2 x 22F 6.3V
Applications
ASIC/CPU/DSP Core Voltages POL Power Supplies DDR Power Supplies Base-Station Power Supplies Fiber Power Supplies Telecom Power Supplies Network Power Supplies
MONOTONIC SS SELECTION POWER-GOOD OUTPUT
COMP
MODE
FB
PWRGD
LX
BST
LX
LX
LX
COMPENSATION
Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
LX
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator MAX8566
ABSOLUTE MAXIMUM RATINGS
EN/SS, EN, IN, SYNC, SKIP, VDD, LSS, PWRGD to GND ..........-0.3V to +4V (4.5V nonswitching) SYNCOUT, SS, COMP, FB, REFIN, FREQ to GND .........................................-0.3V to (VDD + 0.3V) LX Current (Note 1) .................................................-12A to +12A BST to LX .................................-0.3V to +4V (4.5V nonswitching) PGND to GND .......................................................-0.3V to +0.3V Continuous Power Dissipation (TA = +85C) 32-Pin Thin QFN (derate 33.3mW/C above +70C) .....2666.7W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: LX has internal clamp diodes to PGND and IN. Applications that forward bias these diodes should take care not to exceed the IC's package power-dissipation limits.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = 0C to +85C, typical values are at TA = +25C, unless otherwise noted.)
PARAMETER IN/VDD IN and VDD Voltage Range LSS Voltage Range IN Supply Current VDD Supply Current Total Shutdown Current into IN and VDD VDD Undervoltage-Lockout Threshold BST Shutdown Supply Current PWM COMPARATOR Comparator Propagation Delay COMP Clamp Voltage, High Slew Rate Shutdown Resistance ERROR AMPLIFIER FB Regulation Voltage Error-Amplifier Common-Mode Input Range VCOMP = 1V to 2V, VDD = 2.5V and 3.3V VDD = 2.3V to 2.6V VDD = 2.6V to 3.6V Error-Amplifier Maximum Output Current 0.594 0 0 0.8 0.6 0.606 VDD 1.65 V VDD 1.7 mA V From COMP to GND, VEN = 0V VIN = 2.3V to 3.6V, VFB = 0.7V 1.80 0.75 2.0 1.4 30 100 2.15 V V/s 10mV overdrive 20 ns VIN = VDD = VBST = 3.6V, VLX = 3.6V or 0V, VEN = 0V TA = +25C TA = 0C to +85C 0.05 10 A Quiescent current, VFB = 0.7V fS = 1MHz, no load Quiescent current, VFB = 0.7V fS = 1MHz, VLSS = VDD VIN = VDD = VLSS = (VBST - VLX) = TA = +25C 3.6V, VEN = 0V TA = 0C to +85C LX starts/stops switching, 2s deglitch VDD rising VDD falling 1.72 2.3 2.3 0.7 14 1.8 16 50 3 2.0 1.90 2.2 4 3.6 3.6 2.2 V V mA mA A V CONDITIONS MIN TYP MAX UNITS
2
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High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = 0C to +85C, typical values are at TA = +25C, unless otherwise noted.)
PARAMETER FB Input Bias Current REFIN Input Bias Current CONDITIONS VFB = 0.7V, TA = +25C VREFIN = 0.6V, TA = +25C VDD = 2.3V to 2.6V REFIN Common-Mode Range VDD = 2.6V to 3.6V LX (ALL PINS COMBINED) On-Resistance, High Side On-Resistance, Low Side Current-Limit Threshold Leakage Current ILX = -2A ILX = 2A VIN = VBST - VLX = 3.3V VIN = VBST - VLX = 2.5V VIN = VLSS = 3.3V VIN = VLSS = 2.5V 12 VLX = 3.6V VLX = 0V RFREQ = 50k RFREQ = 23.3k -200 0.8 1.7 87 8 12 8 12 15 5 +5 1 2 50 95 10 10 0.4 1.65 VDD = 2.3V to 3.6V Monotonic start No monotonic start 0.01 5 8 8 30 1.90 45 20 1 11 0.7 1.2 2.3 75 16 20 16 20 20 200 A m m A 0 0 MIN TYP 40 70 MAX 200 250 VDD 1.65 VDD 1.7 UNITS nA nA
MAX8566
V
VIN = 2.5V or 3.3V, high side VIN = 3.6V, VEN = 0V, TA = +25C VIN = 2.5V or 3.3V VIN = 2.5V or 3.3V RFREQ = 50k, VIN = 2.5V or 3.3V RFREQ = 50k, VIN = 2.5V or 3.3V
Switching Frequency Minimum Off-Time Maximum Duty Cycle Minimum Duty Cycle RMS LX Output Current ENABLE/SOFT-START EN Input Logic-Low Threshold EN Input Logic-High Threshold MODE Input Threshold EN, MODE Input Current Soft-Start Charging Current SS Discharge Resistance
MHz ns % % A V V % of VDD A A k
VEN = VMODE = 0V or 3.6V, VDD = 3.6V, TA = +25C VSS = 0.3V
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3
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator MAX8566
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = 0C to +85C, typical values are at TA = +25C, unless otherwise noted.)
PARAMETER SYNC Capture Range Pulse Width Input Threshold Input Current SYNCOUT Frequency Range Phase Shift from SYNC or Internal Oscillator Output Voltage THERMAL SHUTDOWN Thermal-Shutdown Threshold Thermal-Shutdown Hysteresis POWER GOOD Threshold Voltage Falling-Edge Deglitch Output Low Voltage Leakage Current IPWRGD = 4mA VPWRGD = 3.6V, VFB = 0.9V, TA = +25C VFB falling, 3mV hysteresis 86 30 90 50 0.15 0.01 93 80 0.3 1 % of VREFIN or 0.6V s V A When LX stops switching +165 20 C C VDD = 2.3V to 3.6V Frequency = 1MHz ISYNCOUT = 1mA, VDD = 2.3V to 3.6V VOH VOL 0.25 160 VDD 0.4 180 VDD 0.05 0.05 0.4 2.40 230 MHz Degrees VDD = 2.3V to 3.6V VDD = 2.3V to 3.6V VDD = 2.3V to 3.6V VSYNC = 0V or 3.6V, VDD = 3.6V tLO tHI VIH VIL IIH IIL, TA = +25C -1 -1 +0.01 0.25 100 100 0.4 0.95 1 1.6 +10 +1 2.40 MHz ns V A CONDITIONS MIN TYP MAX UNITS
V
4
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High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator
ELECTRICAL CHARACTERISTICS
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = -40C to +85C, unless otherwise noted. Note 2)
PARAMETER IN/VDD IN and VDD Voltage Range LSS Voltage Range IN Supply Current VDD Supply Current VDD Undervoltage-Lockout Threshold COMP Clamp Voltage, High Slew Rate Shutdown Resistance ERROR AMPLIFIER FB Regulation Voltage Error-Amplifier Common-Mode Input Range Error-Amplifier Maximum Output Current VDD = 2.325V to 2.5V REFIN Common-Mode Range VDD = 2.6V to 3.6V LX (ALL PINS COMBINED) On-Resistance, High Side On-Resistance, Low Side Current-Limit Threshold ILX = -2A ILX = 2A VIN = 2.5V or 3.3V VIN = VBST - VLX = 3.3V VIN = VBST - VLX = 2.5V VIN = VLSS = 3.3V VIN = VLSS = 2.5V 12 16 20 15 20 20 m m A 0 VCOMP = 1V to 2V, VIN = 2.3V or 3.6V VDD = 2.325V to 2.6V VDD = 2.6V to 3.6V 0.591 0 0 0.8 0 VDD 1.65 VDD 1.7 V 0.609 VDD 1.65 VDD 1.7 V From COMP to GND, VEN = 0V VIN = 2.3V to 3.6V, VFB = 0.7V 1.80 0.75 100 2.18 V V/s Quiescent current, VFB = 0.7V Quiescent current, VFB = 0.7V LX starts/stops switching, 2s rising/falling-edge delay VDD rising VDD falling 1.72 2.325 2.325 3.600 3.600 2.2 4 2.2 V V mA mA V CONDITIONS MIN TYP MAX UNITS
MAX8566
V
mA
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5
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator MAX8566
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = -40C to +85C, unless otherwise noted. Note 2)
PARAMETER Switching Frequency Minimum Off-Time Maximum Duty Cycle RMS Output Current ENABLE/SOFT-START EN Input Logic-Low Threshold EN Input Logic-High Threshold MODE Input Threshold EN, MODE Input Current Soft-Start Charging Current SYNC Capture Range Pulse Width Input Threshold VIN = 2.3V to 3.6V VIN = 2.3V to 3.6V VIN = 2.3V to 3.6V tLO tHI VIH VIL 0.25 100 100 0.4 1.6 2.40 MHz ns V VIN = 2.3V to 3.6V Monotonic start No monotonic start 5 1.65 30 45 20 1 12 0.7 V V % of VDD A A VIN = 2.5V or 3.3V VIN = 2.5V or 3.3V RFREQ = 50k, VIN = 2.5V or 3.3V 87 10 CONDITIONS RFREQ = 50k RFREQ = 23.3k MIN 0.8 1.7 TYP MAX 1.2 2.3 90 UNITS MHz ns % A
VEN or VMODE = 0V or 3.6V, VDD = 3.6V VSS = 0.3V
6
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High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = -40C to +85C, unless otherwise noted. Note 2)
PARAMETER SYNCOUT Frequency Range Phase Shift from SYNC or Internal Oscillator Output Voltage POWER-GOOD Threshold Voltage Falling-Edge Deglitch PWRGD Output Voltage IPWRGD = 4mA VFB falling, 3mV hysteresis 85 30 93 80 0.3 % of VREF s V VDD = 2.3V to 3.6V Frequency = 1MHz ISYNCOUT = 1mA, VDD = 2.3V to 3.6V VOH VOL 0.25 160 VDD 0.4 0.4 2.40 230 MHz Degrees CONDITIONS MIN TYP MAX UNITS
MAX8566
V
Note 2: Specifications to -40C are guaranteed by design and not production tested.
Typical Operating Characteristics
(Typical values are at VIN = VDD = 3.3V, VOUT = 1.8V, RFREQ = 50k, IOUT = 10A, and TA = +25C.)
EFFICIENCY vs. LOAD CURRENT VIN = VLSS = 3.3V
MAX8566 toc01
EFFICIENCY vs. LOAD CURRENT VIN = VLSS = 2.5V
MAX8566 toc02
EFFICIENCY vs. LOAD CURRENT VIN = 2.5V, VLSS = 3.3V
95 90 EFFICIENCY (%) 85 80 75 70 65 60 VOUT = 0.8V VOUT = 1.5V VOUT = 1.8V
MAX8566 toc03
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 0.1 1 10 VOUT = 2.5V
100 95 90 EFFICIENCY (%) VOUT = 1.8V VOUT = 1.5V
100
VOUT = 1.8V
85 80 75 70 65 60
100
0.1
1
10
100
0.1
1
10
100
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
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7
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator MAX8566
Typical Operating Characteristics (continued)
(Typical values are at VIN = VDD = 3.3V, VOUT = 1.8V, RFREQ = 50k, IOUT = 10A, and TA = +25C.)
REFERENCE VOLTAGE vs. TEMPERATURE
MAX8566 toc04
FREQUENCY vs. TEMPERATURE
MAX8566 toc05
LOAD REGULATION
0.05 OUTPUT VOLTAGE CHANGE (%) 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 VOUT = 0.8V VOUT = 2.5V VOUT = 1.8V
MAX8566 toc06
0.65 0.64 REFERENCE VOLTAGE (V) 0.63 0.62 0.61 0.60 0.59 0.58 0.57 0.56 0.55 -40 0 40 TEMPERATURE (C) 80 120
2.5 RFREQ = 23.3k 2.0 FREQUENCY (MHz)
0.10
1.5 RFREQ = 50k 1.0 RFREQ = 100k 0.5
0 -40 -15 10 35 60 85 TEMPERATURE (C)
-0.40 0 1 2 3 4 5 6 7 8 9 10 LOAD CURRENT (A)
SHUTDOWN SUPPLY CURRENT vs. INPUT VOLTAGE
MAX8566 toc07
MAXIMUM OUTPUT CURRENT vs. OUTPUT VOLTAGE
MAX8566 toc08
EXPOSED PADDLE TEMPERATURE vs. LOAD CURRENT
EXPOSED PADDLE TEMPERATURE (C) 120 TA = +85C 70 TA = +25C 20 TA = -40C -30 MAX8566 EV KIT PC BOARD 200LFM 0 2 4 6 8 10
MAX8566 toc09
10 SHUTDOWN SUPPLY CURRENT (A) 9 8 7 6 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VEN = 0V
15.0 14.5 14.0 OUTPUT CURRENT (A) 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0
-80 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 OUTPUT VOLTAGE (V)
4.0
INPUT VOLTAGE (V)
LOAD CURRENT (A)
LINE REGULATION
OUTPUT SHORT-CIRCUIT CURRENT (A) 0.4 OUTPUT VOLTAGE CHANGE (%) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 ILOAD = 4.5A ILOAD = 10A ILOAD = 0A
MAX8566 toc10
OUTPUT SHORT-CIRCUIT CURRENT vs. INPUT VOLTAGE
9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 2.25 2.45 2.65 2.85 3.05 3.25 3.45 3.65 3.85 INPUT VOLTAGE (V)
MAX8566 toc11
0.5
10.0
INPUT VOLTAGE (V)
8
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High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator
Typical Operating Characteristics (continued)
(Typical values are at VIN = VDD = 3.3V, VOUT = 1.8V, RFREQ = 50k, IOUT = 10A, and TA = +25C.)
MAX8566
GAIN/PHASE OF THE VOLTAGE LOOP
MAX8566 toc12
LOAD TRANSIENT (0 TO 5A)
MAX8566 toc13
147 kHz 0dB GAIN (10dB/div) VOUT AC-COUPLED (50mV/div)
5A 56 0 PHASE (45/div) 1 10 100 1000 IOUT (2A/div) t = 10s/div 0
FREQUENCY (kHz)
FULL-LOAD SWITCHING WAVEFORMS
MAX8566 toc14
STARTUP INTO 0.18 LOAD (RLOAD = 0.18)
7A (PEAK) IIN (5A/div) 0A 3.3V VOUT (10mV/div) 3V VLX (2V/div) 0V VEN (2V/div) 0V 1.8V VOUT (1V/div)
MAX8566 toc15
IL 12A (2A/div) 10A
3V 0V VPWRGD 0V (2V/div) t = 400s
0A t = 400ns/div
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9
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator MAX8566
Typical Operating Characteristics (continued)
(Typical values are at VIN = VDD = 3.3V, VOUT = 1.8V, RFREQ = 50k, IOUT = 10A, and TA = +25C.)
SOFT-START WITH REFIN
MAX8566 toc16
SYNCHRONIZED OPERATION (NO LOAD)
MAX8566 toc17
6.5A IIN (5A/div) 0A
VREFIN 0.6V (500mV/div) 0V 1.8V VOUT (1V/div) 0V
IIN (AC-COUPLED) (20mA/div) 0A IL1 (2A/div) IL2 (2A/div) 0A 3V VPWRGD (2V/div) 0V t = 400s/div VLX1 (5V/div) VLX2 (5V/div) 3.3V 0V 3.3V 0V t = 400ns/div
SOFT-START TIME vs. SOFT-START CAPACITANCE
MAX8566 toc18
STARTUP INTO PREBIASED OUTPUT (RLOAD = 0.18)
7.5A IIN (PEAK) (5A/div) 0A 3.3V VEN (12V/div) 0V 1.8V VOUT 0.9V (1V/div) 0V
800 700 SOFT-START TIME (ms) 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9
MAX8566 toc19
3V VPWRGD (2V/div) 0V t = 400s
10
CSS (F)
10
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High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator
Pin Description
PIN 1 2 NAME MODE COMP FUNCTION Monotonic Startup Enable/Disable. Connect MODE to GND or to the center tap of an external resistordivider to enable/disable monotonic startup mode. Error-Amplifier Output. Connect the necessary compensation network from COMP to FB. COMP is internally pulled to GND when the IC is in shutdown mode. Power-Good Output. Open-drain output that is high impedance when VFB 90% of 0.6V. Otherwise, PWRGD is internally pulled low. PWRGD is internally pulled low when the IC is in shutdown mode, VDD is below the UVLO threshold, or the IC is in thermal shutdown. High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.1F capacitor. BST is connected to LSS through an internal pMOS switch. Inductor Connection. All LX pins are internally connected together. Connect all LX pins to the switched side of the inductor. LX is high impedance when the IC is in shutdown mode. Power Ground. All PGND pins are internally connected. Connect all PGND pins externally to the power ground plane. Input Power Supply. All IN pins are internally connected. Connect all IN pins externally to an input supply from 2.3V to 3.6V. Bypass IN to PGND with 20F of ceramic capacitance. Low-Side MOSFET-Driver Supply Voltage. Connect to a 2.3V to 3.6V supply voltage. IC Supply Voltage Input. Connect VDD to IN through an external 2 resistor. Bypass VDD to GND with a 4.7F capacitor. External Reference Input. Connect to an external reference. FB regulates to the voltage at REFIN. Connect REFIN to SS to use the internal reference. Soft-Start Input. Connect a capacitor from SS to GND to set the soft-start time. See the Soft-Start section. Enable Input. Active-high logic input to enable/disable the MAX8566. Connect to IN to enable the IC; connect to GND to disable the IC. Synchronization Input. Synchronize to an external clock with a frequency of 250kHz to 2.4MHz. Leave SYNC unconnected to disable the synchronization function. Oscillator Frequency Selection. Connect a resistor from FREQ to GND to select the switching frequency. See the Frequency Select section. Oscillator Output. The SYNCOUT output is 180 out-of-phase from the internal oscillator or the SYNC signal to facilitate running a second regulator 180 out-of-phase with the first to reduce input ripple current. Analog Circuit Ground Feedback Input. Connect to the center tap of an external resistor-divider from the output to GND to set the output voltage. Exposed Paddle. Connect to a large ground plane for increased thermal performance.
MAX8566
3
PWRGD
4 5-12 13-17 18-22 23 24 25 26 27 28 29 30 31 32 --
BST LX PGND IN LSS VDD REFIN SS EN SYNC FREQ SYNCOUT GND FB EP
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11
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator MAX8566
VDD
EN
SHUTDOWN CONTROL
UVLO CIRCUITRY
CURRENT-LIMIT COMPARATOR ILIM THRESHOLD
BST
BIAS GENERATOR
LX
IN P VOLTAGE REFERENCE LSS N
SS
CONTROL LOGIC SOFT-START THERMAL SHUTDOWN ERROR AMPLIFIER N
LX
REFIN FB COMP
+ -
PWM COMPARATOR + OSCILLATOR
PGND LSS MODE FREQ SYNC SYNCOUT
COMP LOW DETECTOR SHDN PWRGD FB
MAX8566
0.54V
N
GND
Figure 1. Functional Diagram
12
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High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator
Detailed Description
The MAX8566 high-efficiency, voltage-mode switching regulator is capable of delivering up to 10A of output current. The MAX8566 provides output voltages from 0.6V to (0.87 x VIN) from 2.3V to 3.6V input supplies, making it ideal for on-board point-of-load applications. The output voltage accuracy is better than 1% over load, line, and temperature. The MAX8566 features a wide switching frequency range, allowing the user to achieve all-ceramic-capacitor designs and faster transient responses. The high operating frequency minimizes the size of external components. The MAX8566 also features a wide 2.3V to 3.6V input voltage range, making it ideal for point-ofload applications with both 3.3V and 2.5V input voltages. The MAX8566 is available in a small (5mm x 5mm), 32-pin thin QFN package. The SYNCOUT function allows end users to operate two MAX8566s at the same switching frequency with 180 out-of-phase operation to minimize the input ripple current, consequently reducing the input capacitance requirements. The REFIN function makes the MAX8566 an ideal candidate for DDR and tracking power supplies. Using internal low-RDS(ON) (8m) n-channel MOSFETs for both highand low-side switches maintains high efficiency at both heavy-load and high-switching frequencies. In addition, the MAX8566 features a low-side-driver supply input (LSS) to boost the efficiency with a higher driver voltage (3.3V) for 2.5V input applications. The MAX8566 employs the voltage-mode control architecture with a high bandwith (> 10MHz) error amplifier. The voltage-mode control architecture allows above 2MHz switching, reducing board area. The op-amp voltage error amplifier works with Type 3 compensation to fully utilize the bandwidth of the high-frequency switching to obtain fast transient response. Adjustable soft-start time provides flexibilities to minimize input startup inrush current. An open-drain power-good (PWRGD) output goes high when VFB reaches 0.54V. low-side MOSFETs. The break-before-make logic and the timing for charging the bootstrap capacitors are calculated by the controller logic block. The error signal from the voltage error amplifier is compared with the ramp signal generated by the oscillator at the PWM comparator and thus the required PWM signal is produced. The high-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp voltage exceeds the VCOMP signal or the current-limit threshold is exceeded. The low-side switch is then turned on for the remainder of the oscillator cycle.
MAX8566
Current Limit
The internal, high-side MOSFET has a typical 15A peak current-limit threshold. When current flowing out of LX exceeds this limit, the high-side MOSFET turns off and the synchronous rectifier turns on. The synchronous rectifier remains on until the inductor current falls below the low-side current limit. This lowers the duty cycle and causes the output voltage to droop until the current limit is no longer exceeded. The MAX8566 uses a hiccup mode to prevent overheating during short-circuit output conditions. The device enters hiccup mode when V FB drops below 420mV and the current limit is reached. The IC turns off for 3.4ms and then enters soft-start. If the short-circuit condition remains after the soft-start time, the IC shuts down for another 3.4ms. The IC repeats this behavior until the short-circuit condition is removed.
Soft-Start and REFIN
The MAX8566 utilizes an adjustable soft-start function to limit inrush current during startup. An 8A (typ) current source charges an external capacitor connected to SS to increase the capacitor voltage in a controlled manner. The soft-start time is adjusted by the value of the external capacitor from SS to GND. The required capacitance value is determined as: C= 8A x t SS 0.6V
Principle of Operation
The controller logic block is the central processor that determines the duty cycle of the high-side MOSFET under different line, load, and temperature conditions. Under normal operation, where the current limit and temperature protection are not triggered, the controller logic block takes the output from the PWM comparator and generates the driver signals for both high-side and
where tSS is the required soft-start time in seconds. The MAX8566 also features an external reference input (REFIN). The IC regulates FB to the voltage applied to REFIN. The internal soft-start is not available when using an external reference. A method of soft-start when using an external reference is shown in Figure 2. Connect REFIN to SS to use the internal 0.6V reference.
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13
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator MAX8566
High-Side MOSFET Driver Supply (BST)
R1 REFIN R2 C
MAX8566
The gate-drive voltage for the high-side, n-channel switch is generated by a flying-capacitor boost circuit. The capacitor between BST and LX is charged from the VLSS supply while the low-side MOSFET is on. When the low-side MOSFET is switched off, the stored voltage of the capacitor is stacked above LX to provide the necessary turn-on voltage for the high-side internal MOSFET.
Frequency Select (FREQ)
Figure 2. Soft-Start Implementation with External Reference
Undervoltage Lockout (UVLO)
The UVLO circuitry inhibits switching when V DD is below 2V. Once VDD rises above 2V, UVLO clears and the soft-start function activates. A 100mV hysteresis is built in for glitch immunity.
The switching frequency is resistor programmable from 250kHz to 2.4MHz. Set the switching frequency of the IC with a resistor from FREQ to GND (RFREQ). RFREQ is calculated as: RFREQ = 50k 1 x - 0.05s 0.95s fs
Monotonic Startup Modes (MODE)
When starting up into a precharged output, the MAX8566 does not discharge the output prior to entering soft-start (known as monotonic startup). Drive MODE to 1/3 of VDD to enable monotonic startup mode. Connect MODE to GND to disable monotonic startup mode.
where fS is the desired switching frequency in Hz.
SYNC Function (SYNC, SYNCOUT)
The MAX8566 features a SYNC function that allows the switching frequency to be synchronized to any frequency between 250kHz to 2.4MHz. Drive SYNC with a
C5 0.047F
C24 OPEN VIN 2.3V TO 3.6V C1 10F C2 10F R1 10 C3 0.22F
23 18 19 20 21 22
LSS IN IN IN IN IN
BST LX LX LX LX LX LX LX LX PGND PGND PGND PGND PGND FB
4 5 6 7 8 9 10 11 12 17 16 15 14 13 32 R7 16.9k
L1 0.47H C6 22F C7 22F
VOUT 1.8V AT 10A
2.4k
R4 100 3300pF C8 120pF
24 R2 20k C4 1F 3 27 R17 20k 1 25 R18 10k R3 50k 28 29
VDD
MAX8566
R5 24.9k
POWER-GOOD OUTPUT
PWRGD EN
R6 12.4k
MODE REFIN SYNC FREQ GND 31
COMP
2
C9 330pF
SYNCOUT SS
30 26 C11 0.022F C10 22pF
Figure 3. Typical Application Circuit. 14 ______________________________________________________________________________________
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator
square wave at the desired synchronization frequency. A rising edge on SYNC triggers the internal SYNC circuitry. The frequency of the input into SYNC must be higher than the internal oscillator frequency set by RFREQ. Leave SYNC disconnected to disable the function and operate on the internal oscillator. The MAX8566 has a SYNCOUT output that generates a clock signal that is 180 out-of-phase with its internal oscillator, or the signal applied to SYNC. This allows for another regulator to be synchronized 180 out-of-phase to reduce the input ripple current.
Inductor Design
Choose an inductor with the following equation: L= VOUT x (VIN - VOUT )
MAX8566
fs x VIN x LIR x IOUT(MAX)
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high impedance once the soft-start ramp has concluded, provided V FB is above 0.54V. PWRGD pulls low when V FB is below 0.54V for at least 50s. PWRGD is low during shutdown.
where LIR is the ratio of the inductor ripple current to average continuous current at the minimum duty cycle. Choose the LIR between 20% to 40% for best performance and stability. Use a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. Powered iron ferrite core types are often the best choice for performance. With any core material the core must be large enough not to saturate at the peak inductor current (IPEAK). Calculate IPEAK as follows: LIR IPEAK = 1+ x IOUT(MAX) 2
Low-Side MOSFET Driver Supply (LSS)
The MAX8566 provides an external input for the lowside MOSFET driver supply (LSS). This allows for higher gate-drive voltages to maximize converter efficiency at low input voltages.
Output Capacitor Selection
The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage rating requirements. These affect the overall stability, output ripple voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitor's ESR, and the voltage drop due to the capacitor's ESL. Calculate the output voltage ripple due to the output capacitance, ESR, and ESL as: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL) where the output ripple due to output capacitance, ESR, and ESL are: VRIPPLE(C) = IP-P 8 x COUT x fs VRIPPLE(ESR) = IP-P x ESR
Shutdown Mode
Drive EN to GND to shut down the IC and reduce quiescent current to 4A. During shutdown, the output is high impedance. Drive EN high to enable the MAX8566.
Thermal Protection
Thermal-overload protection limits total power dissipation in the device. When the junction temperature exceeds T J = +165C a thermal sensor forces the device into shutdown, allowing the die to cool. The thermal sensor turns the device on again after the junction temperature cools by 20C, causing a pulsed output during continuous overload conditions. The soft-start sequence begins after a thermal-shutdown condition.
Applications Information
VDD Decoupling
To decrease the noise effects due to the high switching frequency and maximize the output accuracy of the MAX8566, decouple VDD with a 4.7F capacitor from VDD to GND and a 2 resistor from VDD to VIN. Place the capacitor as close to VDD as possible.
I VRIPPLE(ESL) = P-P x ESL t ON IP-P x ESL, whichever is greater. or VRIPPLE(ESL) = t OFF
______________________________________________________________________________________
15
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator MAX8566
The peak inductor current (IP-P) is: V -V V IP-P = IN OUT x OUT fs x L VIN Use these equations for initial capacitor selection. Determine final values by testing a prototype or an evaluation circuit. A smaller ripple current results in less output voltage ripple. Since the inductor ripple current is a factor of the inductor value, the output voltage ripple decreases with larger inductance. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The low ESL of ceramic capacitors makes ripple voltages negligible. Load-transient response depends on the selected output capacitance. During a load transient, the output instantly changes by ESR x ILOAD. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. After a short time (see the Typical Operating Characteristics), the controller responds by regulating the output voltage back to its predetermined value. The controller response time depends on the closed-loop bandwidth. A higher bandwidth yields a faster response time, preventing the output from deviating further from its regulating value. See the Compensation Design section for more details. determines the zero. The double pole and zero frequencies are given as follows: fP1_ LC = fP2 _ LC = 1 R + ESR 2 x L x C O x O RO + RL
fZ _ ESR =
1 2 x ESR x CO
where RL is equal to the sum of the output inductor's DCR and the internal switch resistance, RDSON. A typical value for R DSON is 8m. R O is the output load resistance, which is equal to the rated output voltage divided by the rated output current. ESR is the total equivalent series resistance of the output filtering capacitor. If there is more than one output capacitor of the same type in parallel, the value of the ESR in the above equation is equal to that of the ESR of a single output capacitor divided by the total number of output capacitors. The high switching frequency range of the MAX8566 allows the use of ceramic output capacitors. Since the ESR of ceramic capacitors is typically very low, the frequency of the associated transfer-function zero is higher than the unity-gain crossover frequency, fC, and the zero cannot be used to compensate for the double pole created by the output filtering inductor and capacitor. The double pole produces a gain drop of 40dB and a phase shift of 90 degrees per decade. The error amplifier must compensate for this gain drop and phase shift to achieve a stable high-bandwidth closed-loop system. Therefore, use Type 3 compensation as shown in Figure 4. Type 3 compensation possesses three poles and two zeros with the first pole, fP1_EA, located at 0 frequency (DC). Locations of other poles and zeros of the Type 3 compensation are given by: 1 2 x R1 x C1 1 fZ2 _ EA = 2 x R3 x C3 fZ1_ EA = 1 2 x R1 x C2 1 fP3 _ EA = 2 x R2 x C3 fP2 _ EA = The above equations are based on the assumptions that C1>>C2, and R3>>R2, which are true in most applications. Placement of these poles and zeros is
Input Capacitor Selection
The input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the IC. The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source but are instead shunted through the input capacitor. High source impedance requires high input capacitance. The input capacitor must meet the ripple-current requirement imposed by the switching currents. The RMS input ripple current is given by: IRIPPLE = ILOAD x VOUT x (VIN - VOUT ) VIN
where IRIPPLE is the input RMS ripple current.
Compensation Design
The power transfer function consists of one double pole and one zero. The double pole is introduced by the output filtering inductor, L, and the output filtering capacitor, C O . The ESR of the output filtering capacitor
16
______________________________________________________________________________________
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator
to provide adequate phase boost. Set the two zero frequencies to 80% of the LC double-pole frequency. Hence:
L LX
MAX8566
R1 =
R2
1 x 0.8 x C1 1 x 0.8 x R3
L x CO x (RO + ESR) RL + RO L x CO x (RO + ESR) RL + RO
MAX8566
R3 FB R1 COMP C1 R4 C3
C3 =
Set the second compensation pole, fP2_EA, at fZ_ESR yields: C2 = CO x C1 x ESR R1 x C1- CO x ESR
C2
Figure 4. Type 3 Compensation Network
Set the third compensation pole at 1/2 of the switching frequency to gain some phase margin. Calculate R2 as follows: R2 = 1 x C3 x fS
determined by the frequencies of the double pole and ESR zero of the power transfer function. It is also a function of the desired closed-loop bandwidth. The following section outlines the step-by-step design procedure to calculate the required compensation components. Begin by setting the desired output voltage. The output voltage is set using a resistor-divider from the output to GND with FB at the center tap (R3 and R4 in Figure 4). Use 20k for R4 and calculate R3 as: V R3 = R4 x OUT - 1 0.6V The zero-cross frequency of the closed-loop, fC, should be less than 20% of the switching frequency, fS. Higher zero-cross frequency results in faster transient response. It is recommended that the zero-cross frequency of the closed loop should be chosen between 10% and 20% of the switching frequency. Once fC is chosen, C1 is calculated from the following equation: C1 = 20 x VIN R fC x 2 x x R3 x 1+ L RO
The above equations provide accurate compensation when the zero-cross frequency is significantly higher than the double-pole frequency. When the zero-cross frequency is near the double-pole frequency, the actual zero-cross frequency is higher than the calculated frequency. In this case, lowering the value of R1 reduces the zero-cross frequency. Also, set the third pole of the Type 3 compensation close to the switching frequency if the zero-cross frequency is above 200kHz to boost the phase margin. Please note that the value of R4 can be altered to make the values of the compensation components practical. The recommended range for R4 is 10k to 50k.
PC Board Layout Considerations and Thermal Performance
The MAX8566EVKIT provides an optimal layout and should be followed closely. For custom design, follow these guidelines: 1) Place decoupling capacitors (VDD and SS) as close to the IC as possible. Keep the power ground plane (connected to PGND) and signal ground plane (connected to GND) separate.
Due to the underdamped nature of the output LC double pole, set the two zero frequencies of the Type 3 compensation less than the LC double-pole frequency
______________________________________________________________________________________
17
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator MAX8566
OPEN-LOOP GAIN COMPENSATION TRANSFER FUNCTION DOUBLE POLE GAIN (dB) THE SECOND POLE POWER-STAGE TRANSFER FUNCTION THE THIRD POLE
THE FIRST AND SECOND ZEROS
f
Figure 5. Transfer Function for Type 3 Compensation
2) Connect input and output capacitors to the power ground plane; connect all other capacitors to the signal ground plane. 3) Keep the high-current paths as short and wide as possible. Keep the path of switching current short and minimize the loop area formed by LX, the output capacitors, and the input capacitors.
4) Connect IN, LX, and PGND separately to a large copper area to help cool the IC to further improve efficiency and long-term reliability. 5) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the IC as possible. 6) Route high-speed switching nodes away from sensitive analog areas (FB, COMP).
18
______________________________________________________________________________________
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator
Pin Configuration
PROCESS: BiCMOS
IN IN IN IN IN PGND LSS VDD
Chip Information
MAX8566
TOP VIEW
24
REFIN SS EN SYNC FREQ SYNCOUT GND FB
23
22
21
20
19
18
17 16 15 14 13
PGND PGND PGND PGND LX LX LX LX
25 26 27 28 29 30 31 32 1
MODE
MAX8566
12 11 10 9
2
COMP
3
PWRGD
4
BST
5
LX
6
LX
7
LX
8
LX
THIN QFN
______________________________________________________________________________________
19
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator MAX8566
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
XXXXX
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
H
1
2
20
______________________________________________________________________________________
QFN THIN.EPS
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX8566
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 T4055-1
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
0.15
A A1 A3 b D E e k L
DOWN BONDS ALLOWED
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.25 - 0.25 0.20 REF. 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 0.50 BSC. 0.25 0.20 REF. 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 0.50 BSC. 0.25 0.20 REF. 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 0.40 BSC. 0.25 0.35 0.45
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.20
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** ** **
NO YES NO NO YES NO YES NO NO YES YES NO NO YES YES NO NO YES NO NO YES
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 - 0.30 0.40 0.50 16 20 28 32 N 40 ND 4 5 7 8 10 4 5 7 8 10 NE WHHB WHHC WHHD-1 WHHD-2 ----JEDEC L1
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3, AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
3.30 3.40 3.20
** SEE COMMON DIMENSIONS TABLE
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
H
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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